1. Field of the Invention
The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device, which has a transistor for high withstand voltage and a transistor for high speed operation mounted together thereon, and to a method of manufacturing such a semiconductor device.
2. Background Information
Conventionally, semiconductor devices that have two field effect transistors (hereinafter referred to as FETs) having different characteristics such as an FET for high withstand voltage and an FET for high speed operation mounted together on a single chip are known. In the following description, the FET with high withstand voltage will be called a high voltage FET, and the FET for high speed operation, i.e. a FET which is not designed for high withstand voltage, will be called a low voltage FET.
In order to acquire the desired operating characteristics, the low voltage FET does not have the structure for generally realizing high withstand voltage. That is, in order for the high voltage FET and the low voltage FET to satisfy the characteristics each of them requires, parts of their respective structures must be different. For instance, when compared with an MOS (metal-oxide semiconductor) FET designed for high withstand voltage (hereinafter referred to as high voltage MOSFET), a MOSFET designed for low withstand voltage (hereinafter referred to as low voltage MOSFET) has a short gate length and a shallow impurity diffusion distribution in the source and drain regions. On the other hand, the high voltage MOSFET has a comparatively long gate length and a comparatively deep impurity diffusion distribution in the source and drain regions. Furthermore, with respect to the high voltage MOSFET, a distance between a gate electrode and a source electrode and a distance between the gate electrode and a drain electrode are respectively longer than those in the low voltage MOSFET. That is, in the high voltage MOSFET, the distance between the gate electrode and the source electrode/the drain electrode is set to be longer than that in the low voltage MOSFET. In the following description, the region between the source electrode or the drain electrode and the gate electrode will be called an inter-electrode offset region, and the distance between the source electrode or the drain electrode and the gate electrode, i.e. the width of the inter-electrode offset region, will be called an inter-electrode offset distance.
Thus, the high voltage MOSFET has a comparatively broad inter-electrode offset region between the source electrode or the drain electrode and the gate electrode. Thereby, a comparatively strong electrical field (henceforth to be referred to as a high electrical field) generated at the gate electrode can be greatly attenuated in the inter-electrode offset region. For this reason, the high voltage MOSFET is capable of being driven by higher voltage than the low voltage MOSFET.
A manufacturing method of a semiconductor device where such a high voltage MOSFET and a low voltage MOSFET are mounted together on a single chip is disclosed in Japanese Patent Application Laid Open No. H08-46183, which is hereby incorporated by reference. In the following, an example of a conventional manufacturing method of a semiconductor device will be shown. The following example is a case where a p-type substrate is used.
First, in a field region of a p-type silicon substrate, an insulation film provided for element isolation (henceforth to be referred to as field oxide) is formed using a LOCOS (local oxidation of silicon) method, for instance. The regions in which the field oxide is not formed are demarcated as active regions where the elements of the high voltage MOSFET and the low voltage MOSFET will be respectively formed. In the following description, the active region for the high voltage MOSFET will be called a high voltage MOSFET region, and the active region for the low voltage MOSFET will be called a low voltage MOSFET region.
After forming the field oxide as mentioned above, gate insulation films are respectively formed in the surfaces of the high voltage MOSFET region and the low voltage MOSFET region by oxidizing the surfaces of those MOSFET regions. Next, after masking the high voltage MOSFET region by a resist using for example, a photolithography technique, the gate insulation film formed in the low voltage MOSFET region is removed using for example, an etching technique. Then, after removing the resist that has been masking the high voltage MOSFET region, the upper surface of the substrate is oxidized to form in the surface of the low voltage MOSFET region a gate insulation film that is thinner than the gate insulation film in the high voltage MOSFET region.
Then, after forming the gate insulation film on each active region as described above, a polysilicon film is formed on the whole surface of the substrate where the field oxide and the gate insulation films are formed, using a CVD (Chemical Vapor Deposition) method for instance. This polysilicon film is then patterned using for instance, the photolithography technique and the etching technique. Thereby a gate electrode is formed on each gate insulation film.
Next, after masking the low voltage MOSFET region by a resist using for example, the photolithography technique, negative ions (e.g. phosphorous ions) are implanted into the high voltage MOSFET region using for example, an ionic implantation technique. At this time, since the field oxide, the gate electrode and the resist on the low voltage MOSFET region serve as a mask, the negative ion should be implanted in a predetermined region within a high voltage MOSFET region in a self-aligning manner. The predetermined region where the negative ion is implanted turns into a diffusion region.
Next, after removing the resist that has been covering the low voltage MOSFET region, the high voltage MOSFET region is masked by a resist using for example, the photolithography technique. Then, negative ions (e.g. phosphorous ions) are implanted into the low voltage MOSFET region using for example, the ionic implantation technique. At this time, since the field oxide, the gate electrode, and the resist on the high voltage MOSFET region serve as a mask, the negative ions should be implanted in a predetermined region within a low voltage MOSFET region in a self-aligning manner. The predetermined region where the negative ions are implanted turns into a diffusion region. The resist on the high voltage MOSFET region is to be removed after the ionic implantation in the diffusion region of the low voltage MOSFET region.
After forming the diffusion regions by applying ionic implantation in each active region, an insulator made of silicon nitride is deposited using a CVD method for instance, on the whole surface of the substrate where the gate electrodes, the gate insulation films, and the field oxide are formed. Then anisotropic etching is performed on the insulation film formed at this time. Thereby, sidewall spaces are formed on the side faces of the gate electrode in each active region.
Next, highly doped diffusion layers are formed in a part of the diffusion regions of the high voltage MOSFET region (to be referred to as a first region) and in a part of the diffusion regions of the low voltage MOSFET region (to be referred to as a second region). Here the first region is separated from the gate electrode of the high voltage MOSFET region by a predetermined distance, i.e. the inter-electrode offset distance. The highly doped diffusion layers are to function as a source electrode and a drain electrode. In this process, a resist is formed on the region ranging from the gate electrode of the high voltage MOSFET region to the first region, i.e. on the inter-electrode offset region, using for example, the photolithography technique. Then, negative ions are implanted using the ionic implantation technique, for example. At this time, since the resist is on the high voltage MOSFET region, the gate electrodes and their sidewall spacers, and the field oxide serve as a mask, the negative ion should be implanted into a predetermined region (i.e. the first and the second regions) in a self-aligning manner. The resist on the inter-electrode offset region of the high voltage MOSFET region is to be removed after the highly doped diffusion layers are respectively formed in the first and second regions.
In recent years, more miniaturized MOSFETs are being pursued for the purpose of improving the operation speed of the semiconductor device. In this respect, however, there is a problem that parasitic resistance of drain and source electrodes are no longer able to be disregarded.
As a technology for reducing such parasitic resistance, for example, there is a SALICIDE (Self Aligned Silicide) technology. This SALICIDE technology is a technology for siliciding the upper parts of drain, source, and gate electrodes in a self aligning manner.
Specifically, for example, after forming the gate electrode, drain, and source electrodes (highly doped diffusion layers) as described above, a metal with a high melting point, such as cobalt (Co), titanium (Ti), etc. is deposited over the whole upper surface of the substrate where the gate, drain, and source electrodes are formed, and then a thermal treatment is performed on the surface of the substrate where the high melting point metal is deposited. Thereby, heat reaction occurs between the silicon/polysilicon and the high melting point metal, and each surface of the gate, drain and source electrodes is silicided. That is, salicide films are formed in these surfaces. The high melting point metal which did not cause the heat reaction is to be selectively removed, but since the method for this process is well-known, explanation thereof will be omitted here.
However, in case of siliciding the surfaces of the drain and source electrodes of the high voltage MOSFET using the above-described SALICIDE technology, the inter-electrode offset regions which are not covered with the sidewall spaces are also silicided. In other words, salicide films with low resistance are formed between the sidewall spacer and the drain electrode, and between the sidewall spacer and the source electrode, respectively. Therefore, the inter-electrode offset distance in the high voltage MOSFET becomes substantially the same as that of the low voltage MOSFET, meaning that it happens to be specified by the width of the sidewall spacers. This leads to a problem in that high withstand voltage operation becomes difficult.
In this way, in a method of manufacturing a high voltage FET such as a high voltage MOSFET, it is difficult to apply the SALICIDE technology. Accordingly, miniaturization of a kind of semiconductor device having a high voltage FET mounted thereon has been difficult.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved semiconductor device and an improved method of manufacturing a semiconductor device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.